Guarded readout systems



Nov.- 24, 1970 D. F. KENNEDY 3,543,157

- GUARDED BBADOUT SYSTEMS Fne Nov. 26 1968 IJnited States Patent 3,543,157 GUARDED READoUT SYSTEMS ])onald E. I(ennedy, South TomS River, 1Z.lI., aSSignof fo E!eoffonic ASSociafes Ioo., Long Bronoh, l`IlJ., a cotofafion of New Jesey EHed Nov. zo, 19o8, Sef. No. 778,95Z

Inf. CL G01 7/00 U.s. CL 324140 3 ClaimS ABSTRACT oF THE DISCLoSURE This invention Telates to a Teadout SysteIn in an anaog coInputer, and Inore parficularly, to a feadout SySten1 Which greatly Teduces the effectS of leakage resistance, capacity and ion n1igTation of the TeadoIt bus.

Analog ooInputeTS include I1any typeS of coInputing elenlents Which are inteTconnected in accordance With a progfam to simulate the bohavior of a dynamic syStem. vVith the con1puting elementS inteTconnected, it may be desired to Tead out the TesultS pToduced by variouS oneS of the computing elenlents. SpecincaHy, prior aft analog conputeTS have utilized relay systeInS to Selectively connect the outpnt terninalS of coInputing elen1entS in turn t() a voltage Teadout Systenl including at leaSt one diTect coupled readout aInpliner.

The voltage feadout iS connected to the fiXed contact of each output Telay of the computing element by Way of a conln1on buS called the readoUt bus. The oI1tputS of the coInputing elenlentS are connected to the respective Telay n1ovable contactS via a high SerieS reSistance. The series TeSistance sefVeS to liInit the outpIlt cuTTent of the coInp11ting elenent to a Safe value So fhat, Upon diSconnection of a fiSt coInputing eleInent ffon1 the bus, and connection of a Second con1puting eleIlent to the bllS, the Second element Win be protected floIn having a high cur- Tent appHed to itS outpI1t. This protection iS important Since analog con1puting eleInents Such as direct coupled ampHHeTS are characterized by their low output impedance.

A pToblen1 that haS exiSted f()I some tiITle in the analog coInputer TeSultS fron1 the leakage Tesistance, stray capacitance and ion nligration in the Teadout bus itSelf. TheSe leakage coInponentS cause cuTTenf t() 'be dravvn from the output of the computing elements. This current appearS aS a voltage dfop acroSS the series 1 eSiStance vhich canses an inaccuracy in the readoot of the com poting eleInent. FuTthef descTiption of the effects of the leakage of the bus and a n1eanS foI coInpenSating fof thiS leakage iS discloSed in U.S. Paf. No. 3 41Z 34Z, in the nan1e of TonneSSen, a co-vvorke1 of applicant.

In the past, 1eakage TeSiStance vvaS reduced by detailed Selection and asSeInbly of conlponents. RelayS were choSen f()I 1ow leakage coeicients and the prinfed circI1it CardS vvere carefuny pTepared, In addition, the con1pensating network of the aforen1entioned TonneSSen patent WaS eInployed. ThiS appToach bTought the eectS of leakage to an acceptable leve1.

The preSent invention -TedI1ceS the readout leakage buS valueS of prior aft conlputerS by a factor of one thouSand. In priol readout buS theoTy leakage TesiStance, Stray capacitance and ion migration wore developed between the Teadout bUS and ground. 1 he pTeSent invention involveS lifting the ground point and connecting it to an output of the unloading network. ThiS connection is accon1pHShed by:

(1) Connecting all Telay cases to a bus called the Teadout guard bus; and

(Z) Routing copper on the printed ciTcuit caTd around the feadout buS and connecting the conductor thus fofIned to the readout guaTd bus.

The primary cauSeS of such leakage have been iSolated at the Telay and ()n the pTinted cirouit Card which con- Stitutes the computing eleInent. When the Telay iS open or cloSed, cuTTent ovvs between the contactS and t he relay casing via the leakage resistance in the Telay. ()n the pTinted circuit caTd, leakage TesiStance and Stray capacitance iS pTesent between the Teadout buS and the vaTions componentS n1ounted on the card. ThuS, by nlaintaining the Telay caSe at the San1e potential aS the output voltage being conducted by the relay, no cuffent can How betvVeen the caSe and the contacts; and by ToI1ting Copper aTound the Teadout bus and holding the copper at the Sanle potential as the buS, no current can now betWeen the conlponentS and fhe bI1s.

This TeSultS in the potential of the leakage paths being the same as the potential of the readout buS, So that no cI1Trent can be drawn throtlgh the leakage aths; thus, no voltage drop can occu1 acroSS the seTieS Tesistof.

It iS an object of the present invention to incTeaSe the accuracy of an analog conlputeT.

Another obiect of the pTesent invention is to Teduce the effectS of leakage reSistance and stray capacitance on the out ut signal in an analog compUter readout SyStem.

TheSe aS vven aS fuTther objects and advantageS of the invention vvill becoIne apparent ffoIn a Teading of the fonowing speciHcation vvith refeTence to the accompanying dTawingS in Which= The Single ngure is a schematic diagfam of the read 011t SySten1 according to the invention.

In the drawin numeralS 1, 2 denote a luralit of computing elementS in an analog coInputer. These elenlentS afe Shown as opeTational anlplinefs but it vvill be UndeTStood that they could also be potentionleteTS, InultiplieTS etc, The outputS of the coInpUting elenlentS are connected to the fiXed contact of their TeSpective relays 1Z7, Zo zZ for Selective application of the outputS to a readout bns 3 via large valued TeSistofS 1(z, 2 Each of the relayS include a fxed contact, a Inoveable contact and a casing.

The casingS of the relays aTe connected to a buS 4 vvhich iS caHed the Teadout guaTd.

BuseS 3 and 4 are, in actuality, forIned in part, on the printed circuit card and, in part, of electrical cable The tvvo portionS are ioined by an eleotrical connecfoI Shovvn generally at 17. The cable portions are ioined in a tvVisted air and are connected to an unloading netwoTk of the type diSclosed in the aforenlentioned TonneSSen patent. Readout guaTd buS 4 includeS routed copper lc, ZC C Which iS forIned on the pTinfed circuit card SUTTound ing TeadoI1t bus 3. MoTe paTticularly, poTtionS 1c, Zc c of guaTd b11s 4 and a portion of readoUt buS 3 are phySicany etched onto the printed circI1it card conStituting the computing element. The etched conductors afe Teferred to as Touted copper.

The unloading netvVork includes a direct coupled aInplifier 9 having positive feedback and a gain gTeater than one to produce diTect cuTTent unloading. 1eSistor 11 is the inpnt resistof to thiS Stage whHe reSiStor 15 ServeS aS itS feedback TeSiStor. The poSitive feedback network alSo includeS a luTality of netvvorks pfoducing an A.C. gain gfeatef than one to coInpensate foT the diStTib 11ted vVifing capacitance- These netwoTks afe fofnled of reSiStoTS 10, 10, and capacitoTS 1s, 15. 1eSiStoT 16 iS the feedback Tesistof vvhich SupplieS cuffent to the input of the Unloading netwofk.

The outputs of anlplineTS 8 and 9 are connected to input teTIninalS 13 and 14 of a digital voltn1eteT 7. T11e selectio11 of TeSiStots 11, 15 and 1z, 18 is such that the outputS of an1plifieTs 8 and 9 aTe of equal valueS. ZS the an1p1ieTs ate of the inveTting types, thei1 oI1tpUtS aTe thns of opposite polafity.

The out ut of aIn 1ifie 8 is connected to the guad buS 4 via a voltage divideT conSiSting of resist()fs and 6. The digital voltInetef 7 fequifeS as an input voltage, a ITlagnitude gfeatef than the n1agnitude of the voltage at the input of aInplifief 9; thus, the voltage divider is em ployed to dTop the output of an1plifier 8 to a value equal to the input voltage of ampHer 9.

In thiS Inanner, the guaTd bus 4 is n1aintained at the SaTne potential as Teadout buS 3 pfeventing any cUTfent fiovV and feSultant voltage drop ffon1 i11fille11cing the out, put Signal of any selected ConputeT elenlent, since the guaTd bus iS connected to both the elay caSeS and to the Touted coppef.

1 clain1= 1. A Teadout system fof a pluTality of analog coInput ing elen1entS coInpfising= a Teadont bus,

a plllrality of TelayS having casingS, one foI each conlputing e1enent, connected to said readont bllS foT Selective connection of Said elen1entS to said buS,

nleanS connected to Said Teadont bus fo1 pToviding an indication of the out Uts of Said eleInentS,

a Teadout guafd buS in pTOXin1ity to said Teadont bus connected to Said Telay caSingS and to Said indicat ing nleanS, theTeby Inaintaining the saIne potential 4 on Said guaTd bI1s and Teadout bus fof blocking the leakage pathS of said Teadout bl1s.

Z. The Teadout SysteIn of claiIn 1 Wherein Said indi- Cating Ineans includes a nleteT, an Unloading netvvoTk connected betvveen Said n1etef and Said Teadout bnS and a voltage divideT connected betWeen Said network and guard buS So that the signal on said guard buS is the saIne as the Signal on Said feadout bus.

3. A Teadout sySten1 foT an analog coInputer coInpfiS lng:

a plurality of computing elen1ents,

a Teadont bus,

a plurality of Telays each having a casing oonnected betvveen said eleIIlents and said bus foT solectively connecting Said elen1entS to Said buS, an Unloading netWork connected to said bus for pIeventing cuTrent fmm being dfawn fTom said elements when they aTe connected theTeto and for pToviding an output fepTesenting the signa1 on said bUS, a gUafd bus connected to said casings and Suffounding Said Teadout bus, and

a potentionletef connected betvveen the ontput of said Unloading netvvoTk and Said guard bUS to InaintaiI1 the guard bus at the san1e Signal level as said Teadout bllS, theTeby Teducing Teadout bus leakage pathS.

1efe!enceS (:ffed

UNITED STATES PATENTS 3,36L899 1/1968 MaSSen et al 3Z4140 XR 3 41Z 34Z 11/1968 TonneSSen 33076 ALFRED E. SMITH, Primar Examiner 

